1. Field of Invention
The present invention relates to a semiconductor and a method for manufacturing a semiconductor. More particularly, the present invention relates to a high-voltage device and a method for manufacturing a high-voltage device.
2. Description of Related Art
A high voltage device is one of the most important devices utilized in a highly integrated circuit. Erasable programmable read only memory (EPROM) and flash memory are two of the high-voltage devices most often used in computers and electronic products.
Due to the increasing number of semiconductor devices incorporated in integrated circuits, the size of transistors needs to be decreased. Accordingly, as the channel length of the transistors is decreased, the operating speed is increased. However, the short channel effect caused by the reduced channel length is becoming serious. If the voltage level is fixed as the channel length is shortened, the strength of the electrical field is increased according to the equation, electrical field=electrical voltage/channel length. Thus, as the strength of the electrical field increases, the energy of electrons increases and electrical breakdown is likely to occur.
In the conventional high-voltage device, the formation of an isolation layer is used for the purpose of increasing the channel length. Hence, the high-voltage device is able to work normally at a high electrical voltage.
FIG. 1 is a schematic, cross-sectional view of a conventional high-voltage device. As shown in FIG. 1, a field oxide layer 102 is located on a P-type substrate 100. A gate oxide layer 103 is located on the P-type silicon substrate 100. A gate electrode 104 is located on the field oxide layer 102 and the gate oxide layer 103. A source region 106 and a drain region 108 are located in the P-type substrate 100. An Nxe2x88x92-type doped region 112 is located in the substrate beneath the drain region 108, the field oxide layer 102 and a portion of the gate electrode 104. A P-type doped region 114 is located under the source region 106 and a portion of the gate electrode 104.
In order to increase the breakdown voltage of the high-voltage device, it is necessary to decrease the dopant concentration of the drift region, which is the dopant concentration of the Nxe2x88x92-type doped region 112. However, the current-driving performance and the channel conductivity between the source region 106 and the drain region 108 under the gate electrode 104 in the substrate 100 are decreased.
Additionally, when the manufacturing technique is promoted to a sub-quarter micron level, for example, a line width of 0.18 microns or less, it is difficult to decrease the typical design rule of the high-voltage device.
The invention provides a high-voltage device constructed on a substrate having a first conductive type. The high-voltage device comprise a first well region with the first conductive type, a second well region with a second conductive type, several field oxide layers, several first doped regions with the second conductive type, a shallow trench isolation, a second doped region with the first conductive type, a third well region with the first conductive type, a gate structure, a source region with the second conductive type and a drain region with the second conductive type. The first well region is located in the substrate and the second well region is also located in the substrate but isolated from the first well region. Several field oxide layers are located on a surface of the second well region. One of the field oxide layers is positioned on the margin of the second well region near the first well region. The shallow trench isolation is located between the field oxide layers in the second well region. The first doped regions are located beneath the field oxide layers. The second doped region is located beneath the shallow trench isolation in the second well region. The third well region is located in the first well region and expands from a surface of the first well region into the first well region. The gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers. The source region the drain region are relatively located in the first and the second well regions exposed by the gate structure and the field oxide layers.
The invention also provides a method for forming a high-voltage device. A substrate having a first conductive type is provided. A first well region with the first conductive type is formed in the substrate. A second well region with a second conductive type is formed in the substrate. A pad oxide layer and a patterned silicon nitride layer are formed on the substrate in sequence. Several first doped regions with the second conductive type are formed in the second well region under portions of the pad oxide layer exposed by the patterned silicon nitride layer. Several field oxide layers are formed on the portions of the pad oxide layer above the first doped regions. The patterned silicon nitride layer and the pad oxide layer are removed. A shallow trench isolation is formed in the second well region between the field oxide layers. A third well region with the first conductive type is formed in the first well region while a second doped region with the first conductive type is formed in the second well region beneath the shallow trench isolation. A gate structure is formed on the substrate between the first and second well regions and laterally expands to cover a portion of the first and the third well regions and the field oxide layer. A source with the second conductive type and a drain with the second conductive type are respectively formed in the third well region and the second well region exposed by the gate structure and the field oxide layer.
In the method described above, when the first conductive type is N-type, the second conductive type is P-type. Simultaneously, when the first conductive type is P-type, the second conductive type is N-type. Incidentally, a dosage of the third well region is higher than that of the first well region.
In the invention, around the source region, the first well region contains the third well region. Since the dosage of the third well region is higher than that of the first well region, the depletion region existing between the first and the third well regions is relatively small. According to the equation of electrical field=electrical voltage/channel length, the relatively small depletion region possesses a relatively high electric field. Hence, the conductivity and the electric-field intensity of the high-voltage device are increased. Therefore, the current-driving performance is increased.
Moreover, around the drain region, a depletion region exists between the second doped region and the second well region. Furthermore, the dosage of the second well region is lower than that of the conventional Nxe2x88x92-type doped region 112. Therefore, it can provide a bulk breakdown around the drain region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.